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14 nm工艺3D FinFET器件源漏寄生电阻提取与建模

Extracting and Modeling of Source/Drain Parasitic Resistance of 3D FinFET Devices in 14 nm Process
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摘要 随着CMOS技术进入14 nm技术结点,三维鳍型场效应晶体管(FinFET)源漏寄生电阻的提取随结构的改变而变得更为复杂,高精度寄生电阻的提取对器件建模及电路性能至关重要。根据FinFET器件结构将源漏寄生电阻分割为3部分:由凸起源漏与接触孔所引入的寄生电阻(R_(con))、狭窄鳍到宽源漏区的过渡区寄生电阻(R_(sp))以及源漏与沟道之间的寄生电阻(R_(ext))。考虑电流拥挤效应、电流展宽和栅压控制效应,分别采用平均电流长度法和微元积分法等对R_(con),R_(sp)和R_(ext)进行建模。最后,将所建模型与TCAD仿真进行对比验证,结果表明所建模型可准确反映源漏寄生电阻的变化,其中过渡区寄生电阻的相对误差小于1%。 As CMOS technology continuously enters in the 14 nm technology node, the extraction of source/drain parasitic resistances of 3D fin field effect transistor (FinFET) becomes more complicated as the device structure changes. The high-precision extraction of the parasitic resistance is pretty important to the device modeling and circuit performance. According to the structure of the FinFET device, the source/drain parasitic resistances were divided into three parts, including parasitic resistance induced by the raised source/drain and the contact hole (Rco,,) , the transition region parasitic resistance from the narrow fin to wider source/drain region (R) and the parasitic resistance between source/drain and channel (Rex). Considering the current crowding effect, the current broadening and the gate voltage control effect, R Rsp and Rox, were modeled by means of average current length method and microelement integral method, respectively. Finally, the modeling results were compared with the TCAD simulation results. The results show that the proposed model can accurately reflect the change of the source/ drain parasitic resistance. The relative error for the transition region resistance is less than 1%.
出处 《半导体技术》 CAS CSCD 北大核心 2018年第2期120-124,153,共6页 Semiconductor Technology
基金 国家自然科学基金资助项目(61574056)
关键词 鳍型场效应晶体管(FinFET) 非本征寄生 源漏寄生电阻 建模 TCAD仿真 fin field effect transistor (FinFET) extrinsic parasitic source/drain parasitic resistance modeling TCAD simulation
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