摘要
In this paper TCAD-based simulation of a novel insulated shallow extension （ISE） cylindrical gate all around （CGAA） Schottky barrier （SB） MOSFET has been reported, to eliminate the suicidal ambipolar behavior （bias-dependent OFF state leakage current） of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The IoN/Iovr： of ISE-CGAA-SB-MOS- FET increases by 1177 times and offers steeper subthreshold slope （-60 mV/decade）. However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.
In this paper TCAD-based simulation of a novel insulated shallow extension （ISE） cylindrical gate all around （CGAA） Schottky barrier （SB） MOSFET has been reported, to eliminate the suicidal ambipolar behavior （bias-dependent OFF state leakage current） of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The IoN/Iovr： of ISE-CGAA-SB-MOS- FET increases by 1177 times and offers steeper subthreshold slope （-60 mV/decade）. However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.
基金
UGC,Government of India for providing the necessary financial support
