摘要
The impact of negative bias temperature instability （NBTI） can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps （△ VHT） in gate insulator, generated traps （△ VOT） in bulk insulator, and interface trap generation （△ VIT）. In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor （CMOS） process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.
The impact of negative bias temperature instability （NBTI） can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps （△ VHT） in gate insulator, generated traps （△ VOT） in bulk insulator, and interface trap generation （△ VIT）. In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor （CMOS） process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.
基金
supported by the National Natural Science Foundation of China(Grant Nos.61574056 and 61204038)
the Natural Science Funds of Shanghai,China(Grant No.14ZR1412000)
the Fund from the Science and Technology Commission of Shanghai Municipality(Grant No.14DZ2260800)
Shanghai Sailing Program(Grant No.17YF1404700)
