摘要
VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。本文对VHDL语言综合进程作了详细的讨论,认为综合过程就是将RTL级描述、对设计的电路约束和属性及工艺库这些输入产生一个优化的门级网表。
The logic synthesis of VHDL language is a method that t he description of higher abstract hierarchy is shifted to lower one automatically .In this paper,the pro-cess of VHDL language synthesized is discussed in deta il.It is thought that process synthesized is that the RTL gradation descriptio n,the circuit restriction designed,prop-erty and technology bank are input a nd then a gate gradation netlist optimized will be gained.
出处
《电测与仪表》
北大核心
2002年第8期36-38,57,共4页
Electrical Measurement & Instrumentation
关键词
VHDL
逻辑综合
描述
VHDL
log ic synthesis
description
