摘要
论述了一种适用于低速采样系统采集高频宽带周期信号的高速顺序采样方法 .利用在本地锁相环产生的一个与信号重复周期Trep相近的时钟信号作为采样保持电路的控制信号 ,采样时钟周期Ts 与信号重复周期之间的差值为ΔT =± (Ts-Trep) ,而时间ΔT反映了等效采样的时间分辨力 .探讨了锁相环路的设计和系统触发原理 ,给出了差频采样的原理框图及相应的触发电路 .该方法突破了传统顺序采样在使用商用可编程延时器时的局限性 ,在测控、虚拟仪器。
This paper discusses a high-speed sequential sampling method that is particularly suitable for a low rate sampling system to sample a broadband waveform with a repetitive component. The control signal of sample and its hold circuit is a clock closed to the period of input signal and generated by a local PLL. The offset time between the period of sampling clock and the period of the repetitive component of input signal is ΔT. ΔT represents the timing resolution of the equivalent time sampling system. The designing of PLL and system trigger are discussed. The block diagram of offset frequency sampling and the trigger circuit are presented. The method breaks the restriction of using commercial programmable delay generator in the application of traditional method of sequential sampling. It is useful in many domains, such as measurement, virtual instrument, and signal processing.
出处
《华中科技大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2002年第8期4-6,共3页
Journal of Huazhong University of Science and Technology(Natural Science Edition)
关键词
顺序采样
锁相环
相位抖动
希尔伯特变换
系统触发
sequential sampling
phase locked loop
phase jitter
hilbert transform
system trigger
