摘要
设计了一种基于FPGA的北斗B1频点信号发生器,通过MATLAB对北斗B1频点的C/A码、D码及其被扩频后经过QPSK调制的卫星模拟信号分别进行了仿真,使用Verilog HDL描述了信号发生器,并使用ISE对设计进行综合实现,使用Modelsim对信号发生器内的模块进行仿真.实验结果验证了设计的正确性和可行性,为信号发生器的最终实现提供了强有力的支撑.
The paper is about the design of a signal generator suitable for the signal emission of Beidou on FPGA. A signal generator at Beidou B I frequency point based on FPGA is designed. The C/A code and D code of the Beidou B 1 frequency point by MATLAB and the satellite simulation signals modulated by QPSK after their spreading spectrum are simulated respectively. Verilog HDL is used to describe signal generator and ISE is used to realize the implementation of the whole design. Modelsim is used for the simulation of the modules in the signal generator. The experimental resuhs verify the correctness and feasibility of the de- sign, providing a strong support for the ultimate realization of signal generator.
作者
喻娜
廖雄
罗正华
方安成
YU Na LIAO Xiong LUO Zhenghua FANG Ancheng(School of lnforroation Science and Fngineering, Chengdu University, Chengdu 610106, China Fifth Institute, Telecommunications Science and Technology Resem,ch Institute, Chengdu 610021, China)
出处
《成都大学学报（自然科学版）》
2017年第1期73-75,共3页
Journal of Chengdu University（Natural Science Edition）
基金
成都市科技局科技惠民计划(2015-HM01-00399-SF)资助项目
