摘要
基于电子不停车收费系统(ETC)接收机的要求,在TSMC018μm工艺下设计并实现一种8bit 32 MS/s流水线型模数转换器。通过详细理论分析确定设计参数和电路模型,通过运放共享以及带有增益自举的套筒式运算放大器和开关电容共模反馈电路降低电路的静态功耗,通过动态比较器以及静态锁存结构降低电路的动态功耗,使得功耗降低为原来的一半。测试结果显示ADC输入摆幅-0.4~0.4V下,功耗5.017mA,非使能状态下功耗0.567μA,信噪比(SNR)49.21dB,有效位(ENOB)7.77bit,无杂散噪声(SFDR)65.41dB,面积580μm×450μm。
Based on the design specification of the receiver on ETC, an 8-bit 32MS/s pipelined ADC was designed and implemented using TSMC 0.18μm process. The design parameter and circuit model were determined by detail theoretical analysis. The static power dissipation of the circuit is lowered by amplifier sharing, the use of telescope amplifier with gain-boosting and switch-capacitor common mode feedback, and the dynamic power dissipation is lowered by the use of dynamic comparator with static latch, resulting that the total power dissipation lowered by a factor of two. The test results of the ADC show a operating current of 5. 017 mA under the input range of -0.4-0.4 V, a leakage current of 0. 567μA when the circuit is disable, SNR of 49.21 dB, ENOB of 7.77bit, SFDR of 65.41 dB. The size of the circuit is 580 μm ×450 μm.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2017年第1期52-56,共5页
Research & Progress of SSE
基金
中国自然科学基金资助项目(61376036)
中国专用集成电路与系统重点实验室基金资助项目(2015MS010)
