摘要
根据数字锁相环的原理,本设计用VHDL语言实现了锁相功能。本设计的数字锁相环是由数字鉴相器、数字环路滤波器、数字振荡器,相位调整模块组成。在设计中对锁相时间与相位同步误差做了一定的调整,使本设计中的锁相环具有快速锁相,低同步误差等优点。同时采用模块化设计,使得各个功能模块具有独立性强,修改方便等特点。仿真结果表明:信号经过锁相环以后,能够很快地进入锁定状态并且具有很小的相位误差。
According to the principle of digital phase-locked loop, the design achieves phase locking function with VHDL language. Digital phase locked loop in design is composed of digital phase detector, digital loop filter, digital oscillator and phase adjusting module. For the phase lock time and phase synchronization error, it has done a certain adjustment in the design to make phase locked loop having advantages of fast lock and low synchronization error. At the same time, the use of modular design makes each function module being strongly independent and easily modified. Simulation results show that： the signal can be locked fast and has a very small phase error after phase locked loop.
出处
《乐山师范学院学报》
2016年第8期24-28,共5页
Journal of Leshan Normal University
基金
四川省教育厅科研基金重点项目"软件无线电中的加密模块研究"(15ZA0145)
