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大功率P沟道VDMOS器件设计与工艺仿真 被引量:2

Design and process simulation of high voltage P-channel VDMOS
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摘要 作为现代电力电子核心器件之一的P沟道VDMOS(vertical double-diffuse,MOS)器件,一直以来由于应用领域狭窄而并未得到足够的研究。以P沟道VDMOS器件为研究对象,为一款击穿电压超过-200V的P沟道VDMOS设计了有源区的元胞结构及复合耐压终端结构,并开发了一套完整的P沟道VDMOS专用非自对准工艺流程。最后通过仿真得到器件的击穿电压超过-200V,阈值电压为-2.78V,完全满足了设计要求,也为下一步流片提供了有益的参考。 As one of core devices in modern power semiconductor, P-channel VDMOS device has not been well researched for its narrow applications. We focused on the development of P-channel VDMOS device, designed a P-channel VDMOS with breakdown voltage over -200 V, including the active region cell structure and the junction termination structure, and developed a non-self-aligned progress flow for P channel VDMOS. Simulation results show that the breakdown voltage of the device is over -200 V and the threshold voltage is -2.78 V. The results meet the design requirements, and the research can provide references for the device fabrication.
出处 《重庆大学学报(自然科学版)》 EI CAS CSCD 北大核心 2016年第4期133-138,共6页 Journal of Chongqing University
基金 国家自然科学基金资助项目(61106106) 中央高校基本科研业务费专项基金(K5051325002 K50511250008)~~
关键词 P沟道VDMOS 击穿电压 导通电阻 阈值电压 P-channel VDMOS breakdown voltage on-resistance threshold voltage
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参考文献17

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