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权电容DAC完全响应分析

Analysis of Complete Response for Weighted Capacitor DAC
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摘要 在考虑MOS管开关导通电阻的情况下,对权电容DAC做了复频域分析。分析结果指出,权电容DAC的输出电压信号中仅含有零状态响应,没有零输入响应。在分析中,将每个加权电容-MOS管开关作为一个独立的支路,把二进制数字信号序列作为权电容DAC的输入控制信号,每一个输入数字信号对应于权电容DAC的一个模拟输出电压,且每个输入数字信号保持的时间足以使电路进入稳定状态。由此,建立了一种权电容DAC的完全响应模型,只要二进制数字信号保持的时间足够长,权电容DAC的输出中就不会含有零输入响应分量。这对于分析权电容DAC的各种技术特性具有十分重要的意义。 Considering the gate on resistor of MOS transistor as a switch,the analysis of complex frequency domain（Laplace domain）was done to the weighted capacitor DAC（WCDAC）.The analysis results showed that there was only zero-state response（ZSR）and no zero-input response（ZIR）in the output signal of WCDAC.In analysis,each weighted capacitor-MOS transistor was an independent branch.The sequence of binary digital signal was the input control signal of WCDAC,and each input digital signal was corresponding to an analog voltage which was the output of WCDAC.In addition,each digital signal could be kept for a time enough to make WCDAC get into stable state.Following such an idea,the complete response model of WCDAC in Laplace domain had been built.The model showed that there was no ZIR if and only if the time to hold digital signal was long enough.The result meant that it was no necessary to consider the influence of ZIR during analyzing the parameters and performances of WCDAC.
作者 刘佳 吕彩霞 李哲英 钮文良
机构地区 北京市信息服务工程重点实验室 北京航空航天大学计算机学院 北京联合大学信息学院 北京联合大学应用科技学院
出处 《微电子学》 CAS CSCD 北大核心 2016年第1期128-131,135,共5页 Microelectronics
基金 北京高等学校青年英才计划项目(YETP1773 YETP1754) 北京市信息服务工程重点实验室开放课题资助项目
关键词 复频域 D/A转换器 权电容 MOS Complex frequency domain DAC Weighted Capacitor MOS
分类号 TP335.4 [自动化与计算机技术—计算机系统结构]
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参考文献13

  • 1YEEY S, TERMAN L M, HELLER L G. A two- stage weighted capacitor network for D/A-A/D conversion [J].IEEE J Sol Sta Circ, 1979, 14 (4) : 778-781.
  • 2LYNN L, FERGUSON JR P. A capacitor-based D/A converter with continuous time output for low-power applications [C] // Int Symp Low Power Elec ~ Des. Monterey, CA, USA. 1997: 119-124.
  • 3CHAO Y, LAM Y Y H. An ultra-low energy capacitive DAC array switching scheme for SAR ADC in biomedical applications [C] // IEEE ICICDT. Kaohsiung, China. 2011:1-4.
  • 4SINGH S P, PRABHAKAR A, BHATTCHARYYA A B. C-2C ladder-based D/A converters for PCM codecs[J]. IEEE J Sol Sta Circ, 1987, 22(6) : 1197- 1200.
  • 5KIM H, MIN Y-J, KIM Y. A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array [C] // IEEE EIXSSC. Hongkong, China. 2008: 1-4.
  • 6CHEN Y F, ZHU X L, HIROTAKA T, et al. Split capacitor DAC mismatch calibration in successive approximation ADC [C] // IEEE CICC. San Jose, CA, USA. 2009: 279-282.
  • 7CHEN P, LIU T C. Switching schemes for reducing capacitor mismatch sensitivity of quasi-passive cyclic DAC [J]. IEEE Trans Circ ~ Syst II: Express Briefs, 2009, 56(1): 26-30.
  • 8CHOIR Y K, TSUI C-Y. A low energy two-step successive approximation algorithm for ADC design[C]// IEEE ISCAS. Taipei, China. 2009: 17-20.
  • 9LEE K S, LEE Y M. Switched-capacitor cyclic DAC with mismatch charge compensation [J]. Elec Lett, 2010, 46(13): 902-903.
  • 10SABERI M, LOTFI R, KHALIL M, et al. Analysis of power consumption and linearity in capacitive digital-to-analog converters used in successive approximation ADCs [J]. IEEE Trans Cire ~ Syst I: Regu Pap, 2011, 58(8):1736-1748.
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2016年 第1期

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