摘要
分析巴克码的设计及其相关的特点与原理,用Verilog语言编写相关器,利用FPGA实现13位巴克码相关器,并对其用Modelsim仿真。仿真证明输出了最大功率主副比,有效抑制了旁瓣,并为雷达工程中巴克码的应用提供更坚实的理论基础。
The Barker code and its characteristics and principle are analyzed. The 13-bit Barker code correlator is designed with Verilog language based on the FPGA,and then simulated via the Modelsim. The simulation results indicate that the maximum master-to-slave power ratio is output and the sidelobe is suppressed effectively,providing a solider theoretical foundation for the application of Barker code in radar engineering.
出处
《雷达与对抗》
2015年第4期39-42,共4页
Radar & ECM
关键词
雷达
信号处理
FPGA
巴克码
相关器
旁瓣抑制
radar
signal processing
FPGA
Barker code
correlator
sidelobe suppression
