摘要
在高速电路设计中,动态逻辑电路应用十分广泛。但由于缺乏内在的上拉恢复路径,动态逻辑电路对单粒子效应极其敏感。因此,相比静态逻辑电路,它们在可靠性要求较高的应用中缺乏吸引力。因此,基于版图布局技术,提出了两个抗单粒子效应的动态逻辑电路设计。因为敏感节点之间的电荷共享效应,单粒子瞬态脉冲得到抑制。仿真结果和实验数据验证了它们具有更高的防止单粒子效应错误的能力。
Due to the intrinsic lack of restoring paths, dynamic logic circuits have significant single- event susceptibility, and thus, they are not preferred in applications requiring high reliability when compared to static logic. However, in high speed applications, this circuit family is still very attractive. Therefore, this papers presents two layout-based single-event resilient dynamic logic designs. The resultant SET pulse is suppressed because of charge-sharing in the layout-level. Simulation results verify that they enjoy higher single event tolerance. Experimental results validate the fact that approximately 20%~30% of magnitude reduction in cross-section is achieved for both designs. On the other hand, the increase in single-event performance is achieved at the expense of non-significant power and area overhead.
出处
《电子测试》
2015年第10期36-40,共5页
Electronic Test
基金
国家自然科学基金(61504038)
关键词
动态逻辑
抗辐射加固
单粒子效应
软错误
脉冲窄化
dynamic logic
radiation hardening
single event effect
soft error
pulse quenching
