摘要
设计了二维离散小波变换和快速零树编码的硬件结构 ,实现了一小波图像编码系统。编写了各个模块的 Verilog HDL模型 ,并进行了仿真和逻辑综合。最后用 Altera公司的 CPL D对整个编码系统进行了验证。结果表明 ,设计的硬件结构是正确的 ,可以用来实现小波图像编码系统。
Presents the hardware implementation of a wavelet image coder. It proposes the architectures to achieve 2-D Discrete Wavelet Transform (DWT) and a fast zerotree image coding (FZIC). The Verilog HDL models for 2-D DWT and FZIC are programmed, and extensive simulation has been carried out to optimize the design. The completed design is synthesized to Altera CPLD. The coder has been verified by a demonstration module and the experiment result shows that both the architectures are efficient and suitable for VLSI implementation.
出处
《现代电子技术》
2002年第2期91-96,共6页
Modern Electronics Technique
