摘要
简要介绍电路进化设计的基本原理 ,提出并讨论基于最小项表达式的染色体编码方案和以 RAM查找表为核心的函数级 FPGA原型 ,以及相应的内部进化实现方法 .理论分析和进化实验结果表明 :文中的编码方案与 FP-GA结构相配合可显著地减少运算量 ;基于相应的实验平台进行适应度在线评估 ,可显著提高进化速度、规模和成功率 .
Some basic concepts on the evolvable hardware(EHW) is briefly introduced.A novel chromosome representation scheme for EHW based on the expression of product term of a logical function is presented and discussed,along with a relevant prototype of the function level field programmable gate array(FFPGA),which mainly consists of a core of RAM look up table and several output logic macro cells(OLMC)and can be configured in field to implement various kinds of combinatorial and sequential logic function.Some theoretical analyses and experimental results showed that the novel chromosome representation scheme and the prototype of FFPGA matched very well for lowering the computation demands,and remarkable improvements on speed and realizable size of evolution design can be obtained by online evaluation of fitness using a relevant hardware platform.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2002年第8期735-737.,共3页
Journal of Computer-Aided Design & Computer Graphics
基金
陕西省自然科学基金 ( 99X0 8)资助
关键词
逻辑电路
进化设计
在线评估
可进化硬件
遗传算法
evolvable hardware,genetic algorithm,chromosome representation,function level field programmable gate array
