摘要
讨论了采用ispLSI1 0 1 6构造数字锁相环的基本方法 ,并给出了分频器。
In this paper, the basic method is discussed that to construct a PLL digital frequency synthesizer. And the programs are put forward for programmable counter, swallow counter and phase comparator in Lattice ABLE-HDL language.
出处
《荆州师范学院学报》
2002年第2期44-47,共4页
Journal of Jingzhou Teachers College
关键词
锁相环
可编程计数器
相位比较器
phase-locked loop
programmable counter
phase comparator
