期刊文献+

基于SHARC流水集束型多处理器板研制 被引量:1

SHRAC-Based Pipeline and Cluster Multi-DSP Board Development
在线阅读 下载PDF
导出
摘要 结合某重点工程课题 ,设计和实现了基于 SHARC流水集束型多处理器板即研制出了具有 5个 SHARC的高速并行数字信号处理机。板上处理器数量可实现重配置以获得高的性价比。当板上前端 4个 SHARC用于 FFT时 ,研究和分析了板上前端 4个 SHARC用于 FFT时的三种不同缓冲数据模式下 The SHARC based pipeline and cluster multi DSP board has been developed that is a high speed parallel digital signal processing system with five SHARC chips.A number of SHARC chips on the board can be reconfigured to get a high ratio of Efficiency/cost.The SHARC of the front four SHARC chips on the board as a node is used for FFT,and three different data buffer modes are proposed and analyzed for the time of FFT carried out by each node.
出处 《火力与指挥控制》 CSCD 北大核心 2001年第3期20-23,共4页 Fire Control & Command Control
关键词 SHARC 流水集束型多处理器板 雷达数字信号处理系统 多DSP并行处理 FFT radar digital signal processing system,multi DSP parallel processing,FFT
  • 相关文献

参考文献3

  • 1Kwag.Y K,Park Y C,et al. Adaptive Clutter Map Detector with a Band-selective Velocity Filter in the Multimode Radar Signal Processor Using Array Processing Technique [J]. IEEE 1995 International Radar Conference, Virginia, 1995,674-691.
  • 2Mikael Taveniku. A Multiple SIMD Mesh Architecture for Multi-Channel Radar Processing [C].Proceedings of International Conference on Signal Processing Application & Tchnology, 1996, 1421-1427.
  • 3Joseph A. Sgro. A Highly Scalable Multiprocessor Based on the ADI SHARC DSP[C]. Proceedings of International Conference on Signal Processing Application & Technology, 1997,1396 1400.

同被引文献2

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部