摘要
利用 CPLD/FPGA目标器件设计一个采样控制器 ,按照正确的时序直接控制 ADC0 80 9的工作 ,完成二至十进制的转换并显示采样值。所有这些功能都采用
A sampling controller is designed by using CPLD/FPGA. According to correct time series ,it can directly control the operation of ADC0809, finish the conversion from binary to decimal and display the sampling value .All these functions are described with VHDL language.
出处
《电子工程师》
2002年第2期37-38,64,共3页
Electronic Engineer
