摘要
针对多处理器系统中存储器访问次序与程序执行次序不同而造成存储器的不一致性 ,通过设计仲裁与选择器以及独立于存储单元的硬件号志 ,实现了文中提出的弱一致性模型 。
In order to deal with the inconsistency problem caused by the different orders in memory accessing and program execution in multiprocessor systems, an arbitrator/selector and a memory independent hardware log are designed. This models the inconsistency mechanism, leading to a solution to the problem.
出处
《上海大学学报（自然科学版）》
CAS
CSCD
2001年第5期401-404,共4页
Journal of Shanghai University:Natural Science Edition
