摘要
讨论了组合逻辑电路的时序安全可替换性问题 ,即如何判断一个组合逻辑电路可以替换另一个组合逻辑电路而电路的速度不会降低 .提出了一种新的判断时序安全可替换性的方法 .该方法通过计算组合逻辑电路的延迟特征函数的蕴涵关系来判断时序安全可替换性 ,避免了直接计算电路的精确延迟特征 ,从而提高了算法的效率 。
This paper addressed the problem of timing-safe replaceability for combinative circuits. That is, how to judge the replaceability of one combinative circuit by another circuit without the risk of deteriorating the performance of the former. Presented algorithm judges the timing-safe replaceability of two combinative circuits by comparing their exact delay abstractions. However, with the increase of the scale of combinational circuits, the computation of exact delay abstractions will take a huge amount of CPU time. To overcome this difficulty, a new approach is described in this paper. This new approach judges the timing-safe replaceability of two combinative circuits by comparing the implication relationship between their delay abstraction functions and avoids the computation of the exact delay abstraction. Hence, this new approach is more effective than presented algorithm and well suited for the timing analysis of the large-scale combinative circuits.
出处
《上海交通大学学报》
EI
CAS
CSCD
北大核心
2001年第9期1271-1274,共4页
Journal of Shanghai Jiaotong University
基金
美国国家科学基金资助项目 ( 5 978East Asia and Pacific Program-96 0 2 45 8)
