摘要
研究了基于QuartusⅡ9.0软件的时序逻辑电路设计方法,其中程序设计法采用了Verilog HDL语言。以同步4位二进制可逆计数器为例演示了设计过程,并对设计情况进行了功能仿真,验证了设计的正确性。
The article studied design method of sequential logic circuit based on Quartus Ⅱ 9. 0 software,which adopted the Verilog HDL language programming method. It takes the synchronous 4 bit binary reversible counter as an example to illustrate the design process. And the design of the function simulation verifies the correctness of the design.
出处
《仪表技术》
2014年第6期43-44,共2页
Instrumentation Technology
