2Juin-Ming Lu,Cheng-Wen Wu.Cost and Benefit Models for Logic and Memory BIST.Proc.Design Automation and Test in Europe (DATE 2000).IEEE CS Press,Los Alamitos,Calif.,20000.
3Alvin Jee.Defect-Oriented Analysis of Memory BIST Tests[C].In:.The 2002 IEEE International Workshop on Memory Technology,Design and Testing (MTDT 2002),2002:2～3.
4Michael L.Bushnell,Vishwani D.Agrawal.Essentials of Electronic Testing for Digital,Memory and Mixed-Signal VLSI Circuits[M].Kluwer Academic Publishers,Boston,2000:253～306.
