摘要
Spin-Transfer Torque RAM （STT-RAM） is an emerging non-volatile memory technology that possesses many attractive characteristics such as-high density, low leakage and low read access latency. However, one of the major drawbacks of STT-RAM technology is its long write latency, which impedes its progress for wide spread adoption for on-chip caches compared to the traditional SRAM based caches. By adopting suitable mechanisms that can minimize the latency overhead of STT-RAM writes, it is possible to design energy-efficient and high density caches for CMPs In this talk, I will discuss two complementary techniques to mitigate the write overhead of STT-RAM. The first approach centers on designing an elegant network level solution. This approach is based on the observation that instead of staggering requests to a write-busy STT-RAM bank, the network should schedule requests to other idle cache banks for effectively hiding the latency.
Spin-Transfer Torque RAM （STT-RAM） is an emerging non-volatile memory technology that possesses many attractive characteristics such as-high density, low leakage and low read access latency. However, one of the major drawbacks of STT-RAM technology is its long write latency, which impedes its progress for wide spread adoption for on-chip caches compared to the traditional SRAM based caches. By adopting suitable mechanisms that can minimize the latency overhead of STT-RAM writes, it is possible to design energy-efficient and high density caches for CMPs In this talk, I will discuss two complementary techniques to mitigate the write overhead of STT-RAM. The first approach centers on designing an elegant network level solution. This approach is based on the observation that instead of staggering requests to a write-busy STT-RAM bank, the network should schedule requests to other idle cache banks for effectively hiding the latency.
