摘要
采用直接数字频率合成(DDS)技术设计的Loran-C信号源,具有输出杂散多且难以预测的缺点。基于对DDS基本原理的研究分析,针对DDS输出信号存在的相位舍位杂散问题,对其关键部位的相位累加模块进行优化设计,并基于FPGA技术,在QuartusⅡ环境下完成了对Loran-C信号源的实现与仿真验证。结果表明,通过优化的设计算法能够产生失真小,稳定度好的输出波形,从而验证了该方法抑制杂散的有效性与可行性。
A shortcoming of the Loran-C signal source designed with DDS（direct digital frequency synthesis） technology is that there are much unpredictable spurious signals in the output. According to the basic principle of the DDS and aiming at the spurious signal caused by phase-truncation, we optimized the design of the phase accumulation module, a key part of the direct digital frequency synthesizer. And based on FPGA technology we completed the implementation and simulation/verification of the Loran-C signal source under the Quartus II environment. The results show that an output waveform with small distortion and good stability can be generated through the optimization of the design algorithm, thereby the validity and feasibility of the optimized design method in spurious suppression are verified.
出处
《时间频率学报》
CSCD
2014年第1期41-48,共8页
Journal of Time and Frequency
基金
中国科学院"西部之光"联合学者资助项目(2007LH01)
中国科学院科研装备研制资助项目(YZ201218)
关键词
罗兰-C
直接数字频率合成
相位舍位杂散
相位累加
现场可编程门阵列(FPGA)
Loran-C
direct digital frequency synthesis
spurious signal caused by phase-truncation
phaseaccumulation
FPGA（field programmable gate array）
