摘要
介绍了一种在FPGA上实现的占用硬件资源少但是速度快的有限脉冲响应滤波器结构,新提出的结构不包含乘法器模块,而是采用加法器和移位寄存器替换乘法器模块。采用的方法为对乘法器系数近似为二次幂三项之和,在FPGA上实现的一个7阶有限脉冲响应滤波器表明该方法比传统含乘法器模块的滤波器占用面积减少75%。
A low area and high speed FIR filter implement on FPGA is introuduced. The new architecture has no multiplication module, which is re- placed by adders and shift registers. This is possible because a coefficient approximation is performed, using the algorithm that computes the coefficients like a SOPOT. Compared with the traditional method, the areaof the 7-tap 12 bit FIR filter occupied is 75% smaller.
出处
《电视技术》
北大核心
2014年第5期71-73,112,共4页
Video Engineering
