摘要
实现了对视频图像数据的采集﹑调度﹑实时编码及传输等功能。以FPGA实现的MCU为主控制器,对采集来的视频信号进行数据调度,将编码后的数据经I2C总线发送至上位机软件,同时对读取的码流解码,最终在PC终端上显示。根据硬件平台的结构特性,设计采用流水线结构对系统进行优化,保证了系统运行的高效性,实现了资源的最优化利用。在Xilinx Virtex-5的FPGA上实现并验证,系统可达的最高工作频率为170 MHz,且满足I帧的实时编码要求,实现高精度﹑高可靠性的AVS采编传输系统。
The functions of video image data acquisition, scheduling, real-time coding, transmission and so forth are achieved in this design. With the MCU implemented on FPGA as the master controller, the video signals acquired are scheduled and the encoded data are sent to upper computer software through I2C bus, at the same time the readed code stream are decoded, and finally it is displayed on PC terminal. According to the structure characteris- tics of hardware platform, pipeline architecture is utilized in this design to optimize the system, which ensures the high eglciency of the system operation and the optimal utilization of resources. Implemented and verified on Xilinx Virtex-5 platform, the maximum frequency of the system can be up to 170 MHz, meeting the real-time encoding demand of I frame and achieving the AVS acquisition and encoding transmission system of high accuracy and high reliability.
出处
《电视技术》
北大核心
2014年第3期53-55,59,共4页
Video Engineering
基金
国家自然科学基金项目(60372058
60772101)
