摘要
以电阻电容充放电正反馈网络为基础,设计了具有固定振荡频率的RC振荡电路,设计中考虑了电源电压和温度变化对振荡频率的影响,进行了优化设计,同时利用低压差稳压器(LDO)消除MOS管的沟道调制效应。该振荡电路可作为数字逻辑控制电路的时钟信号,推动电路逻辑的进行,并为延时信号提供时间基准。电路基于华润上华公司(CSMC)0.35μm n阱双层多晶硅和三层金属(DPTM)工艺设计仿真,后仿真和测试结果表明利用该技术设计的RC振荡电路分频后可产生具有较高的精度的37.5 kHz信号,可作为数字逻辑部件的时钟信号源,满足设计要求。
Taking advantages of the positive feedback of charge-discharge characteristics of resistors and capacitors, and taking the influence of power voltage and temperature variations on the oscillator into consideration. At present, the research comes up with an optimized design of an in-buih RC oscillator which has a fixed oscillation frequency under certain circumstances. Meanwhile, low dropout regulator （LDO） is used in the research to eliminate the MOS transistor channel modulation effect. The RC oscillator can be used as clock signal for the digital logic control circuits to promote their performance, and it can provide a reference time for delayed signals. Then the CSMC 0.35μm n well double poly and there layer metal （DPTM） process model is adopted to carry out simulations in the research. The post- simulations and tests show that the RC oscillator circuits designed in the research at present can produce high precision of 37.5 KHz signal after frequency division, so it can make a good clock signal for digital logic components and meet the design requirements.
出处
《半导体技术》
CAS
CSCD
北大核心
2013年第12期905-909,928,共6页
Semiconductor Technology
基金
江苏省自然科学基金BK2012644
