摘要
数字相敏检波(DPSD)算法是一种有效的信号检测方法。针对某些高速采样系统采用现有DSP芯片控制模数转换和进行DPSD算法运算所出现的控制精度不高和运算速度慢等问题,详细分析了DPSD算法,设计了基于FPGA的数字相敏检波算法。该算法解决了控制信号精度不高等问题,满足高速采样系统对运算速度的要求。试验结果表明,基于FPGA的数字相敏检测算法在测试系统中能有较好的检测效果。
For test systems,digital phase sensitive detection （DPSD） algorithm is an important method to detect signals.In some of the high speed sampling systems,the DSP chip is used to control ADC and operate DPSD algorithm,but the control accuracy is low and operation speed is slow.Through analysing DPSD algorithm in detail,the FPDA-based digital phase sensitive detection algorithm is implemented.This method solves the problem of low accuracy of control signal,and meets the requirement of operation speed for high speed sampling system.The experimental result indicates that the FPDA-based algorithm offers better detecting effects in test systems.
出处
《自动化仪表》
CAS
北大核心
2013年第11期13-16,共4页
Process Automation Instrumentation
关键词
数字相敏检波(DPSD)
FPGA
ADC
DSP
测试系统
高速采样系统
Digital phase sensitive detection （DPSD） Field programmable gate array （FPGA）
Analog to digital converter （ADC）
Digital signal processor（DSP）
Test system
High-speed sampling system
