摘要
为了消除谐波采样中的频谱泄露并降低电路实现代价，提出非均匀同步过采样时钟产生方法．该方法使用延时锁定环路产生非均匀时钟，控制谐波采样的过采样间隔．通过合理设计过采样率、非均匀时钟频率的概率分布以及变化周期，使非均匀过采样噪声位于模数转换器输出带宽之外，减小了采样噪声对谐波频谱的调制影响，保证了非均匀时钟是统计意义上跟踪基波频率的同步时钟．过采样和时钟的非均匀特性大幅简化了延时锁定环路的结构，所需延时单元个数从3×10°减少到125．采样数据可以作为同步采样序列直接进行快速傅里叶变换运算，无需消除非均匀采样噪声和频谱泄露的操作．在使用1．6384MHz参考时钟、基波频率为46～54Hz的情况下，63次谐波范围内的谐波幅度和相位测量误差分别小于0．02％和0．031°．
A non-uniform synchronous oversampling clock generation method was proposed to eliminate the spectral leakage and reduce the circuit cost. Non-uniform clock was generated by delay locked loop to control oversampling intervals. Oversampling ratio, probability distribution and variation period of non- uniform clock frequency were properly designed. Non-uniform oversampling noise was allocated beyond the output bandwidth of analog to digital converter. Spectrum modulation by sampling noise was suppressed. The generated non-uniform clock can be treated as synchronized clock tracking the fundamental in statistical meaning. The structure of delay locked loop was simplified by oversampling and non-uniform property. Number of delay cells was reduced from 3x104 to 125. The sampled data can be treated as uniformly sampled one and fast Fourier transform （FFT） can be directly applied, no sampling noise and spectral leakage elimination needed. When 1. 6384 MHz reference clock was used and fundamental varied between 46 to 54 Hz, the amplitude and phase measurement error of harmonics within 63 times fundamental was smaller than 0.02% and 0. 031 degrees respectively.
出处
《浙江大学学报（工学版）》
EI
CAS
CSCD
北大核心
2013年第10期1857-1862,共6页
Journal of Zhejiang University：Engineering Science
关键词
非均匀同步过采样
谐波测量
时钟产生
non-uniform synchronous oversampling
harmonics measurement
clock generation
