摘要
负阻器件由于在电流-电压特性曲线中表现出独特的负微分电阻特性,从而大大增加了单个器件所能实现的逻辑功能.如果将其用于数字逻辑电路设计,尤其是触发器的设计,可有效减少器件的数目.通过分析CMOS工艺负阻器件MOS-NDR及单双稳态转换逻辑单元MOBILE的工作特性,设计了一个时钟上升沿触发的D触发器.采用TSMC 0.18μm工艺对所设计的电路进行HSPICE仿真,仿真结果表明所设计的电路具有正确的逻辑功能.与基于MOS-NDR负阻器件的同类触发器相比,新设计的D触发器具有更稳健的输出和较强的抗干扰能力.
Negative resistance device shows a unique negative differential resistance characteristic in the current-voltage characteristic curve, which significantly increases the function of a single device. If negative resistance device is employed in digital logic circuit design, especially the design of the flip-flop, the number of devices can be reduced. Through analysis of the operating characteristics of CMOS based MOS-NDR negative resistance device and MO- BILE, a clock rising edge triggered D flip-flop is designed. The circuit is verified by HSPICE simulation with TSMC 0.18μm technology and the simulation results show that the proposed design has correct logic function. Compared to the other D flip-flop design based on MOS-NDR, it shows a more robust output and stronger anti-interference ability.
出处
《浙江大学学报（理学版）》
CAS
CSCD
2013年第6期641-645,649,共6页
Journal of Zhejiang University（Science Edition）
基金
国家自然科学基金资助项目(No.61071062)
浙江省自然科学基金资助项目(No.LY13T010001)
