摘要
在研究有关DDR2 SDRAM技术规范的基础上,提出了DDR2 SDRAM控制器的整体架构设计.采用层次设计方法,以功能为单位,将控制器的设计划分为多个功能模块,使用Verilog语言完成控制器各个模块的RTL级设计,利用Chipscope工具对设计进行了功能验证.
Based on the detailed study of DDR2 relevant JEDEC SDRAM technical specifications, the o- verall structure of DDR2 controller is designed. This design uses a hierachical design method, and the control- ler design is divided into several function modules according to its function. It uses the verilog HDL to imple- ment RTL design of all controller modules. As the RTL design completed, Modelsim is used to verify the func- tion of the design.
出处
《中原工学院学报》
CAS
2013年第4期46-49,共4页
Journal of Zhongyuan University of Technology
