摘要
分析了SRAM自定时技术的原理,对40nm工艺条件下的自定时电路进行优化,大幅降低了位线电位差的波动幅度。分析对比了本设计与传统设计在0.7V～1.1V工作电压下的性能,使SRAM的读取速度提高了,功耗降低了,位线电位差增大了。文中SRAM采用SMIC40nm工艺,大小为36KB(X256Y4D36)。
This paper briefly analyzes the principle of SRAM tracking path technology. A new tracking path is proposed in 40nm SRAM to make SRAM work in low voltage while boosting SRAM speed at normal voltage. The performance of the design is compared with that of traditional one at range of 0.7V- 1. IV. In this paper, SRAM size is 36KB （X256Y4D36） in process of SMIC40nm.
出处
《微处理机》
2013年第3期7-9,共3页
Microprocessors
