摘要
讨论了可综合的 Verilog HDL ( Verilog Hardware Description Language)中的数据类型、运算符、表达式、CASE、IF_ ELSE等语法现象到硬件逻辑功能部件实现时的映射关系 .介绍了一种由 Always@( clock event)块和块内的 CASE、IF_
The synthesis Verilog HDL syntax is discussed such as data type, operator, expression, case and if_else statement. It introduce the mapping relation between Verilog HDL statement and hardware implementation .A synthesis hardware implementation model of Synchronous Sequential Circuits is presented .The description of Synchronous Sequential Circuits is composed of always @ (clock event) statement, case statement and if_else statement.
出处
《内蒙古大学学报（自然科学版）》
CAS
CSCD
2000年第5期544-548,共5页
Journal of Inner Mongolia University：Natural Science Edition
