摘要
通过对Δ调制信号特点的分析提出了累加实现Σ-Δ式DAC的数学模型,利用FPGA实现了该数学模型,通过增加两个冗余位简化了电路设计,给出了Verilog实现程序,定量分析了其准确度、抖动性和快速响应特性,并据此给出了滤波器设计方案和应用特点。
The characteristics of △ modulation signal were analyzed, and then the mathematical model of accumulation ∑ - △ DAC was proposed. The FPGA was applied to the realization of the mathematical model. The design on electric circuit was simplified by increasing 2 redundancies. Verilog execution routine was given. Its accuracy,jitter and fast response characteristics were quantitatively analyzed. Based on the analysis, the filter design plan and application characteristics were demonstrated.
出处
《武汉理工大学学报（信息与管理工程版）》
CAS
2013年第2期187-190,共4页
Journal of Wuhan University of Technology：Information & Management Engineering
基金
航空科研基金资助项目(20085584010)
山东省高等学校科技计划基金资助项目(J12LN74)
