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利用FPGA进行VLSI设计功能验证 被引量:3

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出处 《电子产品世界》 2000年第9期62-62,共1页 Electronic Engineering & Product World
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  • 1蔡美琴.MCS-51系列单片机系统及其应用[M].北京:高等教育出版社,1988..
  • 2Khu Avthur. On board programming of CPLDs using ATE [J].Electron Eng,1997,(11):45~46,4
  • 3Ashen D. G,et al. Testing of PLD with faulty resources [C]. IEEE Int workshop Defect Fault Tolerance VLSI Syst. 1997: 76~84
  • 4Miller Warren,et al. New FPGA architecture challenges CPLDs [J]. Electron Eng, 1998, (5)
  • 5Bratt Adrian. Motorola FPAA,present hardware and future trends [C]. IEE Colloq Dig n233, 1998
  • 6Carter William S,Field Programmable gate arrays [J].Printed Circuit Des, 1998, (6)
  • 7Wirthlin Michael J,et al. Improving functional density using run- time circuit reconfiguration [J]. IEEE Trans VLSI Syst, 1998, (6): 247~ 256
  • 8Detz Vaughn,et al. How much logic should go in an FPGA logic block? [J]. IEEE Des Test Comput, Jan-Mar 1998:10~15
  • 9Gokhale Maya,et al. High level compilation for fine grained FPGAs [J]. IEEE Symp FPGAs Custom Comput Mach Proc,1997:165~173
  • 10Miller Julian F,et al. Discovering novel digital circuits using evolutionary techniques [C]. IEE Colloq Dig,n233 1998: 3/1~3/4

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