摘要
总结了在高速PCB板设计中信号完整性产生的原因、抑制和改善的方法。介绍了使用IBIS模型的仿真步骤以及使用CADENCE公司的AllegroSPB软件,支持IBIS模型对反射和串扰的仿真,验证了其改善后的效果,可以直观地看到PCB设计是否满足设计要求,进而指导和验证高速PCB的设计。
Firstly, the reasons that will destroy signal integrity in PCB is concluded and the method will restrain and improve signal integrity is listed. Secondly, the process how to use IBIS model with CADENCE Allegro SPB software is presented. This software can use IBIS models to simulate the reflected and crosstalk. The improvement of signal integrity in PCB is validated clearly, which can meet our design requirement intuitively. And then it can guide the design and validation of high speed PCB.
