摘要
介绍了一种超高速 51 2 /2 56分频器电路的设计 ,其基本结构采用静态主从 D触发器。电路采用先进的单层多晶硅发射极双极工艺制造 ,使用 3μm设计规则 ,电路的最高工作频率达到 2GHz。
A very high speed 512/256 frequency divider has been desig ned A static master-slave D-type flip-fl op is used as the basic structure of the device The circuit is fabricated in adv anced 3-μm single poly-silicon emitter b ipolar process A maximum operating frequ ency of 2-GHz has been achieved for the circuit
出处
《微电子学》
CAS
CSCD
北大核心
2000年第3期147-149,共3页
Microelectronics
关键词
ECL电路
静态分频器
电路设计
ECL circuit
Fr equency divider
Poly-silicon emitter tra nsistor
Bipolar IC
