摘要
对优化超大规模集成（ＶＬＳＩ）缓冲器的功耗进行了研究。对于驱动较大负载，在满足缓冲器延迟限度范围内实现系统功耗的最小化，是提高ＶＬＳＩ缓冲器性能的关键问题之一。文章发展了关于缓冲器信号延迟、功耗和负载间的关系，并给出基于最小延迟基础上缓冲器功耗的优化设计模型和方法。经ＳＰＩＣＥ模拟验证，该模型可有效地降低系统功耗和提高系统工作性能，说明该设计模型是合理和可行的。
Optimal design of VLSI buffers is investigated,which is to achieve desired circuit speed with minimal power consumptions. An analytical relationship among signal delay,power consumption,chip area of the buffer and interconnection load for VLSI systems has been derived. An optimal design technique for high-speed,low power buffers is described. SPICE simulation shows that power consumption of the system can be reduced effectively,and the system performance can be improved by using the optimized buffers.
出处
《微电子学》
CAS
CSCD
北大核心
2000年第4期213-216,共4页
Microelectronics
