摘要
在分析多级CIC滤波器结构和特性的基础上,阐述了一种利用Hogenaue"r剪除"理论通过消除来自前级的一些较低有效位来提高CIC滤波器性能,并完成多级CIC滤波器的高效FPGA实现方法。通过QuartusⅡ时序仿真分析验证了该方法的正确性和可行性,能够满足现代移动通信系统要求,提高了系统运算效率。通过对内部寄存器的位宽进行改进,极大地节约了硬件资源,提高了系统运行速率。
On the basis of analysis of the structure and characteristics of the multi-stage CIC filter, the paper elaborates an efficient FPGA implementation method which uses the Hogenauer ＂cut off＂ theory which can eliminate some of the less signifi-cant bits from the former class to improve the CIC filter performance, and realize a multi-stage CIC filter on FPGA. The timing simulation analysis of Quartus Ⅱ verifies the correctness and feasibility of the method and shows that the method can meet the re-quirements of modern mobile communication system and improve the system operation efficiency. The improvement of the inter-nal register bits wide saves great hardware resources and increases running speed.
出处
《现代电子技术》
2013年第1期61-63,共3页
Modern Electronics Technique
基金
教育部科研项目(Z2011017)
