摘要
本文提出适用于无失真并行数据压缩的超大规模ASIC的逻辑电路设计 .与其他传统的串行或小规模并行无失真数据压缩的硬件或软件方法相比 ,本文的Systolic阵列结构有更好的并行性、实时性和普适性 .对ASIC的时序和功能进行的模拟验证 ,证明了逻辑和电路设计的正确性和有效性 .
This paper presents a new systolic ASIC scheme to implement the undistorted parallel data compression algorithm based on genetic algorithm (GA).In comparison with other traditional sequential or small scale parallel methods of data compression,the proposed systolic scheme has much higher parallelism,real time performance and more suitability.The simulation of timing performance and functionality for the ASIC scheme verifies its correctness and effectiveness.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2000年第9期135-136,共2页
Acta Electronica Sinica
基金
973国家重点基础研究规划项目基金!(No .G1 9990 32 70 7)
国家自然科学基金!(No .697730 37)
关键词
数据压缩
遗传算法
ASIC
脉动阵列
data compression
genetic algorithm
timing simulation
functional simulation
ASIC (Application Specific Integrated Circuit)
