摘要
为满足多输入、多功能抢答器的特殊需求,采用EDA设计方法,设计了16路输入抢答器,具有抢答、计时、报警、电子计分等功能,设计采用VHDL硬件描述语言实现,在FPGA上验证。该方案具有硬件电路简单、设计灵活、功能稳定等优点。
In order to meet the needs of multi-channel responder, the paper applies the EDA design method to design a 16-channel responder with the function of responding, timing, alarming and scoring. The whole design is realized in VHDL and verified with FPGA. The design has the advantages of simple hardware circuit, flexibility, and stability.
出处
《山西电子技术》
2012年第4期47-48,共2页
Shanxi Electronic Technology
