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A 10 Gb/s burst-mode clock and data recovery circuit

A 10 Gb/s burst-mode clock and data recovery circuit
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摘要 We introduce a gated oscillator based on XONR/XOR cells and illustrate its working process. A halfrate BM-CDR circuit based on the proposed oscillator is designed, and the design is implemented in SMIC 0.13 μm CMOS technology occupying an area of 675 ×25 μm2. The measured results show that this circuit can recover clock and data from each 10 Gbit/s burst-mode data packet within 5 bits, and the recovered data pass eye-mask test defined in IEEE standard 802.3av. We introduce a gated oscillator based on XONR/XOR cells and illustrate its working process. A halfrate BM-CDR circuit based on the proposed oscillator is designed, and the design is implemented in SMIC 0.13 μm CMOS technology occupying an area of 675 ×25 μm2. The measured results show that this circuit can recover clock and data from each 10 Gbit/s burst-mode data packet within 5 bits, and the recovered data pass eye-mask test defined in IEEE standard 802.3av.
作者 顾皋蔚 朱恩 林叶 刘文松
机构地区 Institute of RF-&OE-ICs
出处 《Journal of Semiconductors》 EI CAS CSCD 2012年第7期126-130,共5页 半导体学报（英文版）
基金 supported by the Key Technology Research and Development Program of Jiangsu Province,Industry Part,China(No.BE2008128)
关键词 IOG-EPON clock and data recovery BURST-MODE gated voltage-controlled-oscillator frequencylocked loop IOG-EPON clock and data recovery burst-mode gated voltage-controlled-oscillator frequencylocked loop
分类号 TN752 [电子电信—电路与系统]
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参考文献10

  • 1Tanaka K, Agata A, Horiuchi Y. IEEE 802.3av 10G-EPON stan- dardization and its research and development status. J Lightwave Technol, 2010, 28(4): 651.
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  • 3Cho L C, Lee C, Liu S I. A 33.6-to-33.8Gb/s burst-mode CDR in 90 nm CMOS. IEEE International Solid-State Circuits Confer- ence, Digest of Technical Papers, 2007:48.
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Journal of Semiconductors
2012年 第7期

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