摘要
提出了一种实现数字信号处理 (DigitalSignalProcess ,DSP)算法的基于现场可编程门阵列 (FieldPro grammableGateArray ,FPGA)的实现方案 ,在这一方案中 ,采用超大规模集成电路硬件描述语言 (VHDL)来描述设计方案 ,协调了规模和速度两方面的要求 。
An implementing digital signal process(DSP) algorithm scheme based on the field programmable gate array(FPGA) is proposed. In this scheme, the VHSIC hardware description language is adopted to describe the design scheme. Therefore, both requirements of scope and speed are coordinated. The constant modulus algorithm that we adopted has been realized successfully.
出处
《武汉水利电力大学学报》
CSCD
2000年第2期104-107,共4页
Engineering Journal of Wuhan University
基金
湖北省自然科学基金资助 !(2 0 4 980 332 )
关键词
FPGA
VHDL
逻辑综合
并行处理
数字信息处理
field programmable gate array(FPGA)
VHSIC hardware description language(VHDL)
logical synthesis
parallelism
pipeline
