摘要
介绍SM3密码杂凑算法的基本流程,基于现场可编程门阵列(FPGA)平台,设计SM3算法IP核的整体架构,对关键逻辑进行优化设计。选用Cyclone系列器件作为目标器件,与现有算法进行实现比较,结果表明SM3算法IP核耗费较少的逻辑单元和存储单元,具有最高的算法效率,可为密码片上系统产品的开发提供算法引擎支持。
Aiming at SM3 cryptographic Hash algorithm released by state cryptography administration, the general working flow of the algorithm is summarized in this paper. Based on Field Programmable Gate Array（FPGA） platform, the IP architecture of the SM3 is proposed, and the optimization design of its relevant crucial path is discussed. Choosing three Cyclone FPGAs of Altera corporation as the target devices, the fast implementation of the SM3 is achieved and is compared with some other existing research fruits. Comparison results indicate that the IP implementation of the SM3 consumes smaller logic element and memory bit but has higher algorithm performance. It can provide the algorithm engine for the development of cryptography System on Chip（SoC） products in practice.
出处
《计算机工程》
CAS
CSCD
2012年第6期244-246,共3页
Computer Engineering
基金
现代通信国家重点实验室基金资助项目(9140C1106021006)
郑州市科技创新型科技人才队伍建设工程基金资助项目(096SYJH21099)
关键词
密码杂凑算法
片上系统
关键路径
IP核
现场可编程门阵列
cryptographic Hash algorithm
System on Chip（SoC）
crucial path
IP core
Field Programmable Gate Array（FPGA）
