摘要
分析行间转移型面阵电荷耦合器件(CCD)ICX055AL的工作原理和驱动时序,以现场可编程门阵列(FPGA)为硬件设计载体,采用Verilog硬件描述语言(HDL)设计CCD驱动时序,结合CCD时钟驱动芯片CXD1267AN和2片74HC04构建出CCD驱动电路。通过QuartusⅡ软件对其进行仿真分析,并对芯片EP2C5Q208C8进行配置。结果表明,所设计的驱动电路可以满足ICX055AL的各项性能要求,能够产生准确的脉冲信号驱动ICX055AL工作。
The working principle and driving timing of the interline transfer area array charge coupled device（CCD） ICX055AL are analyzed. Field programmable gate array（FPGA） is chosen for the hardware implementation. The driving timing of CCD is described with the hardware description language（HDL） Verilog. By adding a clock driving chip CXD1267AN and two 74HC04 chips, the CCD driving circuit is designed. Function simulation and system analysis are carried out with the software Quartus II. The pro- gram is then used to configure EP2CSQ208C8. The result shows that the driving circuit design can meet the demands of ICX055AL, and pulse signals are accurately generated to drive ICX055AL.
出处
《上海电机学院学报》
2012年第1期38-43,共6页
Journal of Shanghai Dianji University
基金
华侨大学基本科研业务费专项基金项目资助(JB-ZR1107)
