摘要
可重构多处理器阵列上的容错技术可用来重构含有故障单元的处理器阵列,以便获得最大可用的目标阵列。现有的研究成果主要侧重于重构算法的构造,还没有涉及对重构后目标阵列的同步通讯性能的研究。提出了一种改善目标阵列同步通讯性能的电路优化算法,用来降低目标阵列行与行之间通讯的延时,使得相邻两行处理器的通讯尽可能达到同步。实验结果表明,提出的算法对不同大小、不同故障率的阵列都有相应的同步通讯性能的改善。
Fault-tolerant technique for reconfigurable multiprocessor array deals with the issue of reconstruction of the processor array which contains fault units to get the largest available target array. Previous research focused primarily on the reconfiguration algorithm, which does not involve in the study of the synchronous communication performance for reconstructed target array. This paper proposed an optimization algorithm which can improve the performance of the synchronous communication on target array as it reduces the communication delay between neighboring rows for the target array. Experimental results show that the proposed algorithm achieves improvement on communication synchronous performance on processor arrays with different scales and different fault densities.
出处
《计算机科学》
CSCD
北大核心
2012年第3期295-298,F0003,共5页
Computer Science
基金
国家自然科学基金项目(60970016)资助
