摘要
考虑冲击环境下定时器会遇到的问题,并分析了单一的晶体振荡器和谐振振荡器都不能很好地满足抗冲击性和高精度两方面要求,因此提出了一种基于FPGA设计的双振荡定时器。此定时器能有效地解决爆破作业中延时雷管起爆精度和抗冲击性能之间的矛盾。更主要的是CPLD的时序比集成芯片更加容易控制。在FPGA实现,该设计的定时精度达到纳秒级,很好地满足系统性能要求。本方法具有结构简单、成本低、可靠性高、精度高等优点。
A double oscillation timer based on FPGA design was proposed because of the potential problems under shock environment and the insufficient of shock resistance and high precision of single crystal oscillator and resonant oscillators,which could effeciently solve the dilemma between the initiation precision and shock resistance of delay detonator in blasting assignments.Further more,the FPGA pre-programmed are easier to control than integrated chips.It proves thatthe approach could meet the system performance demands commendably on FPGA.The system has the merits of simple and compact structure,low cost,high reliability and high precision.
出处
《电子测试》
2012年第2期42-45,共4页
Electronic Test
