摘要
提出并实现了一种高速缓存的V-LRU RAM单周期清零技术。运行操作系统的CPU在不同任务之间切换时,需要对V-LRU RAM清零。使用传统的计数器依次清空V-LRU RAM的各行,CPU会白白浪费很多个时钟周期。在一个时钟周期对V-LRU RAM清空,可以大大提高CPU的性能。在四路组相联的高速缓存设计中,容量为16k、8k和4k字节时,使用该技术可以将以前的256、128和64个时钟周期降低到只有1个时钟周期。基于SMIC 0.13μm工艺,实现该技术的硬件电路面积为6 312.8μm2,且高速缓存的缺失率保持在非常低的水平。这种技术同样适用于对RAM需要单周期清空的场合。
A technique to clear V-LRU RAM for high performance cache in a single clock cycle was proposed and implemented.The CPU running operating system need to clear V-LRU RAM when switching between different tasks.When traditional counter is used to clear every line of V-LRU RAM one by one,a large number of clock cycles for CPU was wasted.Clearing V-LRU RAM in one clock cycle could significantly improve performance of the CPU.For a 4-way set-associative cache with a capacity of 16-kByte,8-kByte,and 4-kByte,using the proposed technique,the number of clock cycles could be reduced from 256,128 and 64 to only one.The hardware circuit to implement the technology occupied a chip area of 6312.8 μm2 in SMIC＇s 0.13 μm process,and miss rate of the cache kept at a very low level.This technology could also be used for other applications where clearing RAM in a single cycle is needed.
出处
《微电子学》
CAS
CSCD
北大核心
2012年第1期97-101,共5页
Microelectronics
