摘要
研究了JPEG2000中位平面编码算法，提出了适用于显著性传播过程和清除过程的叉形编码路径，使得完成一个4×n条带编码的路径长度缩减为标准的（n＋1）／（2n）。基于该编码路径，设计了两窗口流水线硬件编码结构，该结构通过两个编码窗口流水线滑动在平均每个时钟内完成16个样本点的位平面编码，关键模块采用组合电路实现，避免了时钟消耗和复杂控制，可在位平面间并行进行。给出了系统的整体VLSI架构。FPGA验证结果表明，系统时钟可综合到203．083MHz，处理512×512的灰度图像达276fps，可满足图像实时处理的要求。
Based on the study of the bit plane coding in JPEG2000, the 2-branch coding path for significance propagation pass and cleanup pass was proposed with the aim of reducing the coding path length for a4 × n strip as （n ＋ 1 ）/（2n） of the standard one. Based on the proposed coding path, a hardware structure called 2-window pipeline capable of bit-plane coding 16 bits per cycle on the average by pipeline sliding of 2 coding windows was proposed, whose key module was implemented by combination circuits, avoiding the cycle consumption and the complicated control, while allowing the parallel working between multiple bit planes. The corresponding VLSI architecture of the whole bit plane coder was constructed. The results of the experiment on FPGA shows that the system frequency can be synthesized into 203. 083MHz, which can process 276 frames of 512 × 512 gray image per second, satisfying the re- quirement of realtime image processing.
出处
《高技术通讯》
CAS
CSCD
北大核心
2012年第1期106-111,共6页
Chinese High Technology Letters
基金
863计划（2009AA11Z219）资助项目.
