摘要
采用FPGA可编程逻辑器件和硬件描述语言Verilog实现了时钟IP核数据传输、调时和闹铃等功能设计.在此基础上,分析和讨论IP核功能仿真和优化的方法,并通过Modelsim仿真工具和Design Compile逻辑综合优化工具对设计进行仿真、综合和优化,证明了设计的可行性.
In this paper,FPGA programmable logic devices and hardware description language Verilog were used to implement an IP core with the fuctions such as data transmission,time adjustment,and alarm clock.On that basis,methods of functional simulation and optimization of the IP core were analyzed and discussed,and the feasibility of this design was demonstrated by simulation,synthesize,and optimization through simulating tools modelsim and logic synthesis optimization tools Design Compile.
出处
《福州大学学报（自然科学版）》
CAS
CSCD
北大核心
2011年第6期857-861,共5页
Journal of Fuzhou University(Natural Science Edition)
基金
福建省自然科学基金资助项目(2010J01332)
教育部出国留学人员回国启动基金资助项目(LXKQ201101)
