期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

应用于OFDM之3.1～8.0GHz超宽带接收机前端芯片设计 被引量：1

Design of A 3.1—8.0 GHz UWB Receiver Front-end Chip for OFDM Applications
在线阅读 下载PDF
导出
摘要 使用TSMC 0.18μm CMOS工艺实现3.1～8.0GHz超宽带接收机前端电路芯片设计,并利用ADS软件进行仿真、电路参数调整。电路架构包括:单端输入差动输出之超宽带低噪声放大器、Balun(Balance-unbalance)以及差动输入/输出的超宽带降频混频器,主要特点是在低噪声放大器输出端和混频器之间加入Balun,提升电路性能并减少芯片面积。芯片测试结果:在供给电压1.8V下,频宽为3.1～8.0GHz,S11<-15.3dB,转换增益为24.6dB,功率消耗为37.98mW。包含接脚,芯片面积0.985(0.897×1.098)mm2。 A receiver front-end chip for ultra-wide band systems operating in 3.1-8.0 GHz frequency range was designed and successfully fabricated by TSMC 0. 18 μm CMOS process. All the circuits were simulated and tuned by simulator ADS （advanced design system）. The proposed chip uses the passive Balun to achieve the conversion between LNA and mixer and, the LNA uses the transformer as input matching to achieve low chip area and high performance. The measured results show that at the supply voltage of 1.8 V, the proposed chip is tunable from 3.1 to 8.0 GHz and obtains S, less than -15.3 dB,conversion gain （CGmax） of 24.6 dB and power consumption of 37.98 mW. Including pads,the total chip area is 0. 985 （0. 897× 1. 098） mm2.
作者 黄进芳 谢佩娟 刘荣宜
机构地区 国立台湾科技大学电子工程系 中华电信研究所
出处 《山东科技大学学报（自然科学版）》 CAS 2011年第6期73-79,84,共8页 Journal of Shandong University of Science and Technology(Natural Science)
关键词 超宽带 前端电路 低噪声放大器 混频器 ultra-wide band, front-end circuit low-noise amplifier mixer
分类号 TN792 [电子电信—电路与系统]
  • 相关文献

参考文献11

  • 1ZHENG H,LUONG H C. A 1.5 V 3. 1 GHz-8.0 GHz CMOS synthesizer for 9-Band MB-OFDM UWB transceivers[J]. IEEE Journal of Solid-State Circuits, 2007,42(6) : 1250-1260.
  • 2KOIVISTO T,MAUNU J,TIILIHARJU E. An analog DS-UWB receiver[C]//2007 IEEE International Conference on U1- tra-wideband. Singapore, Sep. 24-26,2007 : 817-822.
  • 3SHI B,CHIA M Y W. A CMOS receiver front-end for 3.1-10.6 GHz ultra-wideband radio[C]//Radar Conference, 2006, 3rd European. Manehester,Sep. 13-15,2006:350-353.
  • 4WU C Y,LO Y K,CHEN M C. A 3.1-10.6 GHz CMOS direct-conversion receiver for UWB applications[C]//13th IEEE International Conference on Electronics,Circuits and Systems. Nice,Dec. 10-13,200611328-1331.
  • 5HARJANI R,CAI L. Inductor less design of wireless CMOS front end[C]//7th International Conference on ASICON '07. Guilin, Oct. 22-25,2007 : 1367-1370.
  • 6SHI B,CHIA M Y W. An ultra-wideband CMOS receiver front-end[C]//Proceedings of the 37th European Conference on Wireless Technology. Munich, Oct. 8-10,2007 : 1042-1045.
  • 7FU C T, KUO C N. 3- 11 GHz CMOS UWB LNA using dual feedback for broadband matching[C]//Radio Frequency Inte- grated Circuits Symposium. San Francisco,June 11-13,2006 :1-4.
  • 8黄进芳,林伟健,刘荣宜.Op Amp共享与移除取样保持电路之低功率管线式ADC芯片设计[J].山东科技大学学报（自然科学版）,2011,30(2):70-79. 被引量：1
  • 9SHI B,CHIA M Y W. A 3-10 GHz 0.13 μm CMOS receiver front-end for MB-OFDM ultra-wide band systems[C]// 2007 IEEE International Conference on Ultra-Wideband. Singapore, Sep. 24-26,2007 : 622-625.
  • 10CHAO S F ,KUO J J, LIN C L, et al. A DC-11.5 GHz low-power, wideband amplifier using splitting-load inductive pea- king technique[J].Microwave and Wireless components letters, 2008,18 (7) :482-484.

二级参考文献8

  • 1GUPTA S K,INERFIELD M A,WANG J.A 1-GS/s 11-bit ADC with 55-db sndr,250-mw power realized by a high bandwidth scalable time-interleaved architecture[J].IEEE Journal of Solid-State Circuits,2006,41(12):2650-2657.
  • 2CAO J M,CHEN Z J,LU W G,et al.A cost-efficient 12-bit 20 Msamples/s pipelined ADC[C]// Proceedings of 2008 9th International Cont'erence on Solid-State and Integrated-Circuit Technology.Shanghai,2008:1961-1964.
  • 3SHU Y S,SONG B S.A 15b-linear,20 MS/s,1.5b/stage pipelined ADC digitally calibrated with signal-dependent dithering[C]//IEEE Symposium on VLSI Circuits Digest of Technical Papers.Honolulu,2006:218-219.
  • 4LI J,ZENG X,XIE L,et al.A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling application[J].IEEE Journal of Solid-State Circuits,2008,43(2):321-329.
  • 5CHIU Y.High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS[D].Berkeley:University of California,2004.
  • 6JOHNS D,MARTIN K.Analog integrated circuit design[M].New York:John Wiley & Sons,Inc.,1997.
  • 7MIN B M,KIM P,BOWMAN P.A 69-roW 10-bir 80-MSample/s pipelined CMOS ADC[J].IEEE Journal of Solid-State Circuits,2003,38(12):2031-2039.
  • 8SUMANEN L.Pipeline analog-to-digital converters for wide-band wireless communications[D].Helsinki:Helsinki University of Technology,2002.

同被引文献2

引证文献1

山东科技大学学报（自然科学版）
2011年 第6期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部